Petaflops Programming: Parallelism, Pain, and Perverse Programming Paradigms
           
Event Type Start Time End Time Rm # Chair  

 

Workshop 10:30AM 5:00PM 42-43 John van Rosendale (Department of Energy), et al.
 
Title:
(General Info)
  Speakers/Presenter:
Organizers: Fred Johnson (DOE Office of Science), Lauren Smith (National Security Agency) , John van Rosendale (DOE Office of Science)

 

Workshop 10:30AM 12:00PM 42-43 John van Rosendale (Department of Energy), et al.
 
Title:
Petaflops Architectures: The 100,000 Processor Challenge
  Speakers/Presenter:
Moderator: Candace Culhane (National Security Agency), Panelists: James Tomkins (Sandia National Laboratories), Ken Miura (Fujitsu Laboratories), William Dally (Stanford University), Mootaz Elnozahy (IBM)

 

Workshop 1:30PM 3:00PM 42-43 John van Rosendale (Department of Energy), et al.
 
Title:
Petaflops Programming Models: Ameliorating Architectural Issues or Exacerbating Them?
  Speakers/Presenter:
Moderator: Burton Smith (Cray), Panelists: Rusty Lusk (Argonne National Laboratory), Hans Zima (University of Vienna and NASA Jet Propulsion Laboratory), Kathy Yelick (UC-Berkeley), Larry Snyder (University of Washington)

 

Workshop 3:30PM 5:00PM 42-43 John van Rosendale (Department of Energy), et al.
 
Title:
Petaflops Applications: Pity the Programmer Trying to Do Actual Applications
  Speakers/Presenter:
Moderator: Alan Laub (UC - Davis), Panelists: Chris Johnson (University of Utah), Mike Merrill (National Security Agency), Theresa Windus (Pacific Northwest National Laboratory), Richard Loft (University Corporation for Atmospheric Research)
             

 

     
  Session: Petaflops Programming: Parallelism, Pain, and Perverse Programming Paradigms
  Title: (General Info)
  Chair: John van Rosendale (Department of Energy), et al.
  Time: Tuesday, November 18, 10:30AM - 5:00PM
  Rm #: 42-43
  Speaker(s)/Author(s):  
  Organizers: Fred Johnson (DOE Office of Science), Lauren Smith (National Security Agency) , John van Rosendale (DOE Office of Science)
   
  Description:
  Petaflop architectures now on the drawing boards will enable a sequence of scientific breakthroughs and herald a new era in computational science. At the same time, many petaflops architectures are likely to challenge systems designers, language developers, and compiler writers in totally new ways. Pity the poor applications programmer at the end of this chain, who will have to live with the mistakes of architects, language developers and compiler writers alike. A certain amount of "pain" in use of petaflops architectures is surely unavoidable – machines with hundreds of thousands of processors and awkward memory models will not be "user friendly." Moreover, some experts believe that the intrinsic unreliability of hardware at the scale envisioned will force adoption of complex checkpoint and recovery strategies. We firmly believe, however, that much of this pain can be ameliorated by clever architects and programming model designers, assuming they evince a depth of understanding and subtlety of approach not universally evident in the past.

Addressing this broad circle of issues, we present a workshop consisting of three successive panels. The first panel will look at architectural trends and the shape of probable architectures at the beginning of the petaflops era. The next panel will look at evolving and expected programming models, and the way language and compiler developers hope to address the challenges posed by petaflops architectures. Finally, in the third panel a set of current users high-end architectures will respond to the material presented during the other panels, and address the question of how well expected architectures and programming models will, in fact, serve the needs of the applications communities. After each panel, the panelists and moderators from the other two panels will be given an opportunity to grill the sitting panel and hold them accountable!

Additional information regarding this workshop can be found at http://www.mcs.anl.gov/SC03ProgWorkshop
  Link: --
   

 

     
  Session: Petaflops Programming: Parallelism, Pain, and Perverse Programming Paradigms
  Title: Petaflops Architectures: The 100,000 Processor Challenge
  Chair: John van Rosendale (Department of Energy), et al.
  Time: Tuesday, November 18, 10:30AM - 12:00PM
  Rm #: 42-43
  Speaker(s)/Author(s):  
  Moderator: Candace Culhane (National Security Agency), Panelists: James Tomkins (Sandia National Laboratories), Ken Miura (Fujitsu Laboratories), William Dally (Stanford University), Mootaz Elnozahy (IBM)
   
  Description:
  In this first panel of the three-part workshop, computer architects will talk about architectural trends and the shape of probable architectures at the beginning of the petaflops era. This panel will focus on the emerging structure of likely petascale architectures, and what will be expected/needed from programming models, languages, and end users to handle such systems. Questions the panelists should address include:

- What architectural features will be easy to exploit and yield good performance?
- What anticipated features will be complex and problematic for language designers, compiler writers and applications programmers alike?
- What "features" will be so complex that only the run-time environment should see them, and could lead to fragile or down right awful performance?
- Will architectures have so much complexity, and require so many levels of parallelism that our programming models need to reflect this same complexity?
- What are the trends?
- What will be the key things that programming models need to address?
  Link: --
   

 

     
  Session: Petaflops Programming: Parallelism, Pain, and Perverse Programming Paradigms
  Title: Petaflops Programming Models: Ameliorating Architectural Issues or Exacerbating Them?
  Chair: John van Rosendale (Department of Energy), et al.
  Time: Tuesday, November 18, 1:30PM - 3:00PM
  Rm #: 42-43
  Speaker(s)/Author(s):  
  Moderator: Burton Smith (Cray), Panelists: Rusty Lusk (Argonne National Laboratory), Hans Zima (University of Vienna and NASA Jet Propulsion Laboratory), Kathy Yelick (UC-Berkeley), Larry Snyder (University of Washington)
   
  Description:
  This panel will look at evolving and expected programming models, and the way language and compiler developers hope to address the challenges posed by petaflops architectures. Given the range of issues such systems are raising, which issues should the programming model attempt to address, and which should be passed on to the end user? Hot-button issues include: how to handle fault tolerance, very deep memory hierarchies, interoperability, coping with tens or hundreds of thousands of threads, the semantics of intelligent memory, and so on. Questions the panelists should address include:

- What ideas look promising to solve some these issues?
- What do future architectures need to incorporate to make it easier for programmers and compilers?
- Is it better to take an evolutionary or revolutionary approach?
- What about engineering/adoption issues?
- Will users adopt new languages?
- Are problem-solving environments be the way to go?
- What hooks does the language community really need in future architectures?
- Is compiler technology up to the task?
  Link: --
   

 

     
  Session: Petaflops Programming: Parallelism, Pain, and Perverse Programming Paradigms
  Title: Petaflops Applications: Pity the Programmer Trying to Do Actual Applications
  Chair: John van Rosendale (Department of Energy), et al.
  Time: Tuesday, November 18, 3:30PM - 5:00PM
  Rm #: 42-43
  Speaker(s)/Author(s):  
  Moderator: Alan Laub (UC - Davis), Panelists: Chris Johnson (University of Utah), Mike Merrill (National Security Agency), Theresa Windus (Pacific Northwest National Laboratory), Richard Loft (University Corporation for Atmospheric Research)
   
  Description:
  In this third panel a set of current users of high-end architectures will respond to the material presented during the other panels, and address the question of how well expected architectures and programming models will, in fact, serve the needs of the applications communities. This panel will also discuss the sociological issue of what level of maturity and usability a language needs in order to be adopted by the HPC community. Speakers in this panel will characterize their applications from the point of view of algorithms, architecture-factors (e.g. cross section bandwidth, cache issues) and programming model/language issues. They should identify the biggest challenges they foresee in exploiting promised petascale systems and their views on the most profitable directions to take in architecture, programming model, systems and compiler research. Questions the panelists should address include:

- What are the biggest challenges you foresee in using petaflops architectures?
- What do programming models need to provide you to allow you to exploit petaflops architectures productively?
- What constructs or abstractions would make it easier for you to map your application on petaflops architectures?
- At what point in the maturity of a new programming language, would you be willing to try a new promising model?
  Link: --